As Complementary Metal Oxide Semiconductors (CMOS) have gotten progressively smaller, power supply voltages have been correspondingly reduced to reduce the deleterious effects of voltage differentials across increasingly smaller device dimensions. However, this reduction, from a nominal 5 volts to 3.3 volts has not occurred simultaneously with all manufacturers. Nor has this reduction occurred in all devices with which other semiconductor devices must communicate. Thus, a Very Large Scale Integrated (VLSI) chip designed to operate at 3.3 volts may need to interface with another chip operating at 5 volts.
To perform the interface properly requires special circuit or device techniques to avoid stress on components designed for 3.3 volts operation. The alternative is added cost for extra manufacturing steps necessary to make devices which can tolerate higher voltages at the input/output circuits for the integrated circuit.
FIG. 1 depicts a typical CMOS output driver. Such an output driver consists of two transistors, a pull-up transistor Q.sub.1 and a pull-down transistor Q.sub.2. Transistors Q.sub.1 and Q.sub.2 are driven by predriver circuits that receive data and enable signals. The predriver circuits are for the most part scaling stages to scale chip device widths (on the order of tens of microns) to off chip device widths (on the order of one thousand microns). The predriver circuits also include the logic to receive an enable signal which causes V.sub.p to go high which shuts off Q.sub.1 and V.sub.n to go low which shuts off Q.sub.2. As used herein, V.sub.p may be referred to as a positive logic input and V.sub.n may be referred to as a negative logic input.
Transistors Q.sub.1 and Q.sub.2 are large transistors that provide the currents that are associated with driving off-chip. When both Q.sub.1 and Q.sub.2 are disabled, the output V.sub.o is free to move between 0 (zero) volts and 3.3 volts, V.sub.p =3.3 V and V.sub.n =0.0 V. However, if the output driver is coupled to a circuit that operates with a logical 1 of five volts, V.sub.o may attempt to exceed 3.3 volts. This presents three problems (in no particular order). First, transistor Q.sub.1 turns on since .vertline.V.sub.o -V.sub.p .vertline..gtoreq..vertline.V.sub.tp .vertline. (the threshold voltage of a PMOS device). Next, the parasitic diode between the drain of Q.sub.1 and the well becomes forward biased. Finally, the voltages across Q.sub.2 are both V.sub.o -V.sub.n .gtoreq.3.3 V and V.sub.o -V.sub.ss .gtoreq.3.3 V.
The last of these problems (regarding the voltages across Q.sub.2) is commonly solved by adding a cascode transistor, Q.sub.3, as shown in FIG. 2. By properly sizing Q.sub.3 and Q.sub.2, voltage V.sub.c can be controlled such that neither Q.sub.3 nor Q.sub.2 is exposed to excessive voltage. However, the addition of Q.sub.3 does nothing to solve the first two problems.
Thus, there remains a need for a CMOS output driver stage that can operate normally with a power supply voltage of 3.3 volts and yet communicate with circuit devices that operate with a power supply voltage of 5 volts.